One type of memory known in the art is Dynamic Random Access Memory (DRAM). DRAM includes at least one array of memory cells. DRAM uses a main clock signal and a data strobe signal (DQS) for addressing the array of memory cells and for executing commands within the memory. The clock signal is used as a reference for the timing of commands such as read and write operations, including address and control signals. The DQS signal is used as a reference to latch input data into the memory and output data into an external device. For a memory write operation, the DQS signal is typically a differential signal provided by a memory controller.
Input data presented on data pad or pins (DQs) is latched into the memory in response to rising and/or falling edges of the DQS signal. Data latched into the memory in response to a rising edge of the DQS signal is referred to as rising edge data, and data latched into the memory in response to a falling edge of the DQS signal is referred to as falling edge data. Input data on the DQs is typically input to a receiver, which compares the input data to a reference voltage (VREF) signal to provide an internal data signal. Therefore, the internal data signal is dependent on the VREF signal. The differential DQS signal is typically input to receivers that generate an internal DQS signal and an internal inverted DQS signal for latching the input data into the memory. Therefore, the internal DQS signal and internal inverted DQS signal are independent of the VREF signal. If the voltage of the VREF signal moves up or down, there is a shift in the propagation delay for the input data. This shift in the propagation delay may affect the setup and hold times of the DQs.